EPROM and EEROM memory arrays are well known and are in wide use in virtually all facets of electronics technology. The most popular device structure for use in fabricating such arrays is the floating gate MOS transistor, wherein an electrically isolated or "floating" gate has charge carriers placed on it or removed from it to program and erase the device. The presence or absence of charge carriers on the floating gate alters the threshold of the memory device and is sensed when the device is read by sensing circuitry which reacts to the presence or absence of current flow in the memory device channel.
As fabrication technology has matured, array densities have increased while device geometries have shrunk to progressively smaller sizes. Manufacturers have been able to fabricate array sizes of 64K to 128K and even 256K arrays are planned.
The achievement of a process having a 100% yield of good parts has been an elusive goal because manufacturers have had to contend with a variety of circuit defects directly related to the manufacturing process itself. Such defects are discovered during testing after fabrication. Where these defects have occurred in memory devices themselves rather than in peripheral circuitry in the array, the industry has been able to respond by providing extra redundant rows or columns of memory devices which may be substituted for defective devices in an array. This technique has allowed manufacturers to achieve a higher yield of good array products.
Another category of defects is known to plague memory arrays of this type; however, these defects do not manifest themselves prior to shipment and customer use of the memory arrays and thus are not discoverable at test following fabrication. Such defects pose a dilemma for both the memory user and the memory manufacturer because they cannot be foreseen other than by statistical prediction.
This class of defects are memory device failures which may be caused by more than one mechanism but nevertheless manifest themselves similarly. Either the affected bit will not program, or it will program erase but will deteriorate due to charge leakage from the floating gate of the memory device. In both cases the ultimate effect is that the bit will be sensed as unprogrammed or erased and there is no known way to predict if and when such a failure will occur. In any given batch of memory array products, perhaps 3% will experience a single or multiple bit failure sometime after approximately 1000 program and erase cycles.
The effects of such bit failures may range from requiring a service call by maintenance personnel for the equipment containing the memory array device to consequences far more serious where the device is installed in military or other hardware in an application demanding high reliability.
In present military and other high-reliability applications utilizing these memory arrays, users have employed various techniques to guard against the possibility that a single or multiple bit failure will jeopardize system integrity. Such techniques include frequent testing and maintenance, replacement of aging devices; use of redundant arrays, and voting schemes or arbitration logic; use of error correcting codes, and use of extra bits at each memory address for parity bits.
Despite the use of these techniques by the prior art for minimizing the possibility of or correcting errors caused by memory device failures there exists a need for a memory array having increased reliability without the need to resort to external circuitry or utilization of extra parity bit space in each byte or extra peripheral circuitry on the memory chip itself. There further exists the need for an array which is immune to single bit failures and most multiple bit failures and which thus may be considered to be fault-tolerant.
Accordingly, it is an object of the present invention to provide a fault-tolerant memory array which is immune to single bit failures.
It is a further object of the present invention to provide a memory array which is immune to most multiple bit failures.
A further object of the present invention is to provide a memory array having 100% redundant memory locations without the need to employ additional on-chip selection circuitry.
Yet another object of the present invention is to provide a memory array which is immune to all single bit failures and most multiple bit failures without the need to employ external circuitry to correct errors caused by such failures.
An additional object of the present invention is to provide a memory array which is immune to all single bit and most multiple bit failures without resort to extra byte width for the purpose of error detection or correction codes.
Another object of the present invention is to provide a memory array which is immune to all single bit failures and most multiple bit failures which may be adapted from existing designs with a minimum of mask and processing changes.
These and other objects of the present invention will become apparent to those of ordinary skill in the art from the following description, drawings and appended claims.